• Improving the first-level cache bandwidth in the Berkeley Out-of-Order Machine 

      Nesset, Erling Feet (Master thesis, 2023)
      Ettersom moderne prosessorer de siste tiårene har truffet minnegapet, har de brukt minne-nivå-parallelisme(MLP) for skjule forskjellen i ytelse mellom prosessoren og minnet. For å utnytte MLP trenger prosessorer nok ...
    • Latency-aware Resource Management in Data Centres 

      Padala, Abhinav (Master thesis, 2020)
      Energy efficiency is a key issue in data centres. Data centres consume half of its maximum power even at low utilisation. In order to improve energy proportionality, machine utilisation is increased by co-locating best-effort ...
    • Q-PRM - A QoS Aware Resource Manager for Colocated Services 

      Sandberg, Jonas; Allport, Michael Moen (Master thesis, 2021)
      Veksten innenfor bruk av skytjenester har ført til at tjenester som er følsomme for forsinkelser i større grad bor i skyen. Disse tjenestene er ofte rettet mot brukere, et faktum som gjør konsvensjonelle energibesparingsmetoder ...
    • Q-PRM - A QoS Aware Resource Manager for Colocated Services 

      Allport, Michael Moen; Sandberg, Jonas (Master thesis, 2021)
      Veksten innenfor bruk av skytjenester har ført til at tjenester som er følsomme for forsinkelser i større grad bor i skyen. Disse tjenestene er ofte rettet mot brukere, et faktum som gjør konvensjonelle energibesparingsmetoder ...
    • TEA: Time-Proportional Event Analysis 

      Gottschall, Björn; Eeckhout, Lieven; Jahre, Magnus (Chapter, 2023)
      As computer architectures become increasingly complex and heterogeneous, it becomes progressively more difficult to write applications that make good use of hardware resources. Performance analysis tools are hence critically ...
    • Time-Proportional Performance Analysis for Out-of-Order Processors 

      Gottschall, Björn (Doctoral theses at NTNU;2024:52, Doctoral thesis, 2024)
      The quest for an increase in processor performance has become difficult due to the inherent power limitations of today’s chips. As processors become more complex with deeper and wider pipelines, out-of-order execution, and ...